Apr 24

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Presentation of the studies thesis “Parallelizing Simulated Annealing for FPGA Placement using Graph

We invite you for the presentation of the studies thesis of Mr. Felix Schmitt on Friday, 27 April 2012.

Topic: “Parallelizing Simulated Annealing for FPGA  Placement using Graphics Processing Units”

This work explores the parallelization of simulated annealing using General Purpose Graphics Processing Units. Simulated annealing is a standard algorithm for the optimization of problems with exponential runtime such as place and route which are important steps of the hardware synthesis for Field Programmable Gate Arrays.
A prototype extension for VPR, GPUplace, has been developed which uses NVIDIA’s CUDA programming approach for parallelization of the Half-Box Window Decomposition placement algorithm. Its implementation as well as optimization strategies are presented. Experimental results are compared with VPR’s reference implementation regarding performance, result quality and annealing characteristics.

Time: 2.00 pm
Location: Faculty of Computer Science, Room no. 1096 (1st floor)

Permanent link to this article: https://gcoe-dresden.de/presentation-of-the-studies-thesis-parallelizing-simulated-annealing-for-fpga-placement-using-graph/